1. Field of the Invention
The present invention relates to a semiconductor device and a method for design of the same, and more particularly to a semiconductor device including a bipolar transistor with an improved emitter region for a large emitter current output as well as a method for design of an emitter region of a bipolar transistor for a large emitter current output.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
A semiconductor device may include plural bipolar transistors which may be classified into different two types, for example, a first type bipolar transistor designed for a high speed performance with a low current output, and a second type bipolar transistor designed for a high current output.
In general, such first type bipolar transistors have a basic emitter size as a unit emitter size of an emitter region. The second type bipolar transistors may have one or more emitter sizes, which are larger than the basic emitter size of the first type bipolar transistors for providing larger current outputs than the first type bipolar transistors. The above larger emitter sizes allow the second type bipolar transistors to operate in wider direct current regions than the first type bipolar transistors.
In the present specification, the term “emitter size” is used and defined to be a size of the emitter region in a second horizontal direction perpendicular to a first direction along which the emitter region is distanced from a base electrode contact region. In some cases, the emitter regions have a rectangle shape in plan view having a longitudinal direction, which is parallel to the second horizontal direction, for which reason the second horizontal direction will, hereinafter, sometime, be referred to as a longitudinal direction.
The above-described second type bipolar transistors have generally been designed based on the above-described first type bipolar transistors, wherein the emitter size of the second type bipolar transistor is decided with reference to the basic emitter size of the first type bipolar transistor in consideration of an intended or required emitter current of the second type bipolar transistor with reference to a basic emitter current as an unit current defined by the basic emitter size of the first type bipolar transistor. On the other hand, the second type bipolar transistors have been designed to have one or more modified emitter sizes which are larger by an intended or desired direct magnification factor than the basic emitter size. A ratio of the modified emitter size of the second type bipolar transistor to the basic emitter size of the first type bipolar transistor will, hereinafter, be referred to as “magnification factor” or “emitter-size magnification factor”. A ratio of the emitter current from the second type bipolar transistor to the basic emitter current from the first type bipolar transistor will, hereinafter, be referred to as “direct current amplification factor”. In the design viewpoint, it is ideal or desirable that the direct current amplification factor would correspond to the magnification factor.
In conclusion, the above-described one or more modified emitter sizes of the second type bipolar transistors may be decided on the basis of the basic emitter size of the first type bipolar transistors. In view of the design process, the first type bipolar transistor may be considered as a basic bipolar transistor with the basic emitter size for output of the basic emitter current as a unit emitter current, while the above-described one or more second type bipolar transistors may be considered to be one or more modified bipolar transistors having one or more modified emitter sizes for outputs of one or more increased emitter currents which are larger than the basic emitter current. The following descriptions with reference to drawings of FIGS. 1A and 1B and FIGS. 2A and 2B will be concerned with typical conventional first type and second type bipolar transistors.
FIG. 1A is a fragmentary plan view illustrative of a conventional typical example of a second type bipolar transistor as a modified bipolar transistor in the prior art. FIG. 1B is a fragmentary cross sectional elevation view, taken along a C—C line shown in FIG. 1A. In these drawings, illustrations of various structures, which are irrelevant to the subject matter of the present invention, are omitted.
In FIGS. 1A and 1B, a bipolar transistor 100 corresponds to the above-described second type bipolar transistor which is designed for output of a larger emitter current. The second type bipolar transistor 100 has the following typical structure. An n+-type buried region 3 is selectively formed over part of a p-type semiconductor substrate 2. An n-type collector region 104 is also selectively formed over both part of the p-type semiconductor substrate 2 and entirety of the n+-type buried region 3. A p-type isolation region 5 is selectively formed over part of the p-type semiconductor substrate 2 to surround and define the n-type collector region 104 in a rectangle region in the plan view. A p-type base region 106 is selectively formed in an upper region of the n-type collector region 104 in a rectangle shape in the plan view. An n+-type emitter region 107 is also selectively formed in the p-type base region 106. A base electrode contact region 61 is also selectively formed in the p-type base region 106, wherein the base electrode contact region 61 is separated from the n+-type emitter region 107 by the p-type base region 106. A collector electrode contact region 41 is also selectively formed in the n-type collector region 104, so that the collector electrode contact region 41 is separated from the p-type base region 106 by the n-type collector region 104.
The n+-type emitter region 107 has a rectangle shape in plan view, which has a longitudinal direction represented by an arrow mark in FIG. 1A. An emitter size in the longitudinal direction of the n+-type emitter region 107 is 2L. The emitter current generally depends on this emitter size 2L. Increase in the emitter size of the n+-type emitter region 107 causes increase in the emitter current. Namely, the second type bipolar transistor 100 has the emitter size of 2L.
FIG. 2A is a fragmentary plan view illustrative of a conventional typical example of a first type bipolar transistor as a basic bipolar transistor in the prior art. FIG. 2B is a fragmentary cross sectional elevation view, taken along a D—D line shown in FIG. 2A. Similarly to FIGS. 1A and 1B, in these drawings, various structures, which are irrelevant to the subject matter of the present invention, are also omitted.
In FIGS. 2A and 2B, a bipolar transistor 200 corresponds to the above-described first type bipolar transistor which is designed for a high speed performance with a low current output. The first type bipolar transistor 200 is different from the above-described second type bipolar transistor 100 only in respective sizes of the emitter, base and collector regions as well as collector and base electrode contact regions in the second horizontal direction represented by an arrow mark.
The emitter size of the first type bipolar transistor 200 is “L” as illustrated in FIG. 2A, which is just one half of the above emitter size “2L” of the second type bipolar transistor 100 shown in FIG. 1A. Respective sizes in the second horizontal direction of the emitter, base and collector regions as well as collector and base electrode contact regions of the first type bipolar transistor 200 are half of the respective sizes of the emitter, base and collector regions as well as collector and base electrode contact regions in the second horizontal direction of the second type bipolar transistor 100.
As described above, in the design viewpoint, the first type bipolar transistor 200 is the basic bipolar transistor for allowing the second type bipolar transistor 100 to be deigned on the basis of or modified from the first type bipolar transistor 200 by a two times enlargement or magnification of the above respective sizes in the second horizontal direction, so that the increased emitter current defined by the modified or enlarged emitter size of the second type bipolar transistor 100 is larger by almost two times than the basic emitter current as a unit emitter current defined by the basic emitter size of the first type bipolar transistor 200.
In the above conventional typical example illustrated in FIGS. 1A and 1B, the magnification factor is only 2. The semiconductor device may, of course, include further modified bipolar transistors in addition to the above-described modified bipolar transistors. The further modified bipolar transistors may have one or more further modified or enlarged emitter sizes different from or larger than the above-described modified and enlarged emitter size, provided that the one or more further modified or enlarged emitter sizes are, of course, larger than the basic emitter size.
The above-described conventional design method would be efficient in designing a large number of various modified bipolar transistors with reference to the basic bipolar transistor. The conventional design method may, however, be effectively applicable as long as the intended or desired emitter-size magnification factor is relatively low. Namely, the conventional method may be inapplicable if the intended or desired emitter-size magnification factor is relatively high.
Increase in the intended or desired emitter-size magnification factor causes decrease in a direct current amplification factor “Hfe”. Namely, if a high value of the magnification factor is intended or desired, then the direct current amplification factor “Hfe” may be dropped and does not correspond to the magnification factor. This undesired decrease in the direct current amplification factor “Hfe” would give rise to a deteriorated accuracy of or a certain decrease of the actually obtained emitter current as compared to the intended or desired emitter current from the second type bipolar transistor. In this case, the modified or enlarged bipolar transistors will exhibit an undesired output of emitter current lower than the intended or required value.
In order to avoid or eliminate the last-described problem or disadvantages, it may be suggested in design processes to make compensation to the influence by the drop of the direct current amplification factor “Hfe”. This compensation is likely to be complicated and difficult, resulting in a remarkable increase in the load to the design work.
In the above circumstances, it is desired that the above-described one or more modified bipolar transistors with the improved emitter region would be free from any substantive drop of the direct current amplification factor “Hfe” upon taking large value of the emitter-size magnification factor. It is, therefore, desired to develop an improved emitter region of the modified bipolar transistors, wherein the improved emitter region is capable of preventing or suppressing any substantive drop of the direct current amplification factor “Hfe” upon taking large value of the emitter-size magnification factor. It is also desired to develop an improved design method for an emitter region of the modified bipolar transistor without any need to make compensation to the influence by the drop of the direct current amplification factor “Hfe” in the designed process.
The followings are the applicant's admitted prior arts which are believed to be informative to describe the state of the art that emitter regions are modified. Each emitter region is divided into plural sub-emitter regions which are aligned in a direction perpendicular to the second horizontal direction for the purpose of avoiding an undesirable concentration of the emitter current. These conventional techniques are, however, incapable of preventing or suppressing any substantive drop of the direct current amplification factor “Hfe” upon taking large value of the magnification factor.
Japanese laid-open patent publication No. 60-227471 discloses a semiconductor integrated circuit device including bipolar transistors, wherein plural emitter first electrode layers have common electrical connection through emitter first and second interconnection layers, while plural base first electrode layers have common electrical connection through a base first electrode layer. This conventional technique is to provide desired interconnection structures for connecting respective electrodes of the bipolar transistors. The interconnection structures are suitable for increasing the density of integration of the semiconductor integrated circuit as well as for preventing such a high current concentration as to cause an undesired secondary breakdown of a power transistor. This conventional technique is irrelevant to the above issue and is incapable of solving the above problem.
Japanese laid-open patent publication No. 61-194774 discloses a high frequency and high output bipolar transistor which includes base regions, emitter regions, base contact regions, emitter metal conductors, and base contact metal conductors, wherein a periphery length of a center-positioned emitter region is shorter than a periphery length of a side-positioned emitter region. This conventional technique is capable of preventing a thermal concentration at a center position of the transistor for allowing the transistor to exhibit a desired stability of operation. This conventional technique is also irrelevant to the above issue and is incapable of solving the above problem.
Japanese laid-open patent publication No. 2-5431 discloses a high frequency and high output semiconductor device, wherein a peripheral-positioned active device region positioned in a peripheral region of a pellet is lower in a total value of respective stabilized resistances than a center-positioned active device region positioned in a center region of the pellet. This conventional technique is to keep a desired uniformity of temperature increase over the respective active device regions for taking a desired thermal balance over positions. This conventional technique is also irrelevant to the above issue and is incapable of solving the above problem.